1. Field of the Invention
The present invention relates to a silicon/oxide/nitride/oxide/silicon (SONOS) memory, a fabricating method thereof, and a memory programming method. More particularly, the present invention relates to a SONOS memory having improved memory integration by controlling the width of a channel region, a fabricating method thereof, and a multi-level memory programming method.
2. Description of the Related Art
Data in a nonvolatile memory such as a flash memory can be electrically erased, programmed, and stored even when electric power is not supplied to the memory. Nonvolatile memory is being increasingly applied to various fields. Flash memory has advantages of both an erasable programmable read only memory (EPROM) and an electrically erasable programmable read only memory (EEPROM). Here, the EPROM has a reduced cell area due to being formed of one transistor, but data must be entirely erased using ultraviolet rays. Data in the EEPROM can be electrically erased, but the EEPROM has a large cell area due to being formed of two transistors. The flash memory, i.e., a flash EEPROM, is a device fabricated to perform the programming method of the EPROM and the erasing method of the EEPROM while including only one transistor.
Examples of a structure of a common flash memory include a NOR structure, in which cells are arranged between a bit line and ground in parallel, and a NAND structure, in which cells are arranged in series. The NOR nonvolatile memory cells and the NAND nonvolatile memory cells have advantages of high-integration and high-speed, respectively, and may thus be applied to techniques requiring these characteristics.
FIG. 1A illustrates a sectional view showing a structure of a conventional flash semiconductor memory. Referring to FIG. 1A, a flash memory having a floating gate structure is formed of a floating gate 17 for storing charges on a semiconductor substrate 11, an oxide/nitride/oxide (ONO) insulating layer 15 formed on the floating gate 17, and a control gate 13 stacked on the ONO insulating layer 15 for controlling the floating gate 17.
As capacities of memories increase and circuits become more complicated, an increased number of gate arrays and micro patterning techniques are required. The size of a conventional stacked gate type nonvolatile memory cell has been reduced; however, photolithography and etch methods for fabricating the memory cell have not followed this trend. In a memory device having a structure of a floating gate for storing charges and a control gate stacked thereon, it is difficult to pattern the memory device due to a high step difference compared to a micro plane size.
FIG. 1B illustrates a sectional view of a conventional stacked gate type nonvolatile memory cell with a floating gate. More specifically, FIG. 1B illustrates a sectional view of a metal/oxide/nitride/oxide/silicon (MONOS) nonvolatile cell of a single gate structure, such as a MOSFET structure. Referring to FIG. 1B, the MONOS cell, or a SONOS cell, uses an ONO insulating layer 25 between a substrate 21 and a control gate 23, instead of a gate oxide, where the ONO insulating layer 25 is substituted for a floating gate. Consequently, silicon nitride (SiN) is formed between thin oxide layers to charge or discharge electrodes to or from the SiN. Here, a thickness of the ONO insulating layer 25 is smaller than 100 to 200 Å, which does not increase the step difference. Thus, it is possible to form the memory cell having a reduced size by a photolithography method, and the structure does not require additional processes related to a floating gate.
A SONOS type memory without a floating gate has been developed by Nisshin Seifun Group Inc. and AMD. Inc. for several years to attain a highly integrated nonvolatile memory (NVM) device. An integration density of a 2-bit memory using an asymmetry programming method is twice that of a stacked gate type flash memory.
FIG. 2A is a graph illustrating changes in threshold voltages VT according to changes in voltages VDS between source and drain electrodes in a 2-bit memory using an asymmetry programming method. FIG. 2B illustrates a sectional view of a 2-bit memory corresponding to line graph f1 of FIG. 2A, and FIG. 2C illustrates a sectional view of a 2-bit memory corresponding to line graph f2 of FIG. 2A.
The same 2-bit memory is illustrated in FIGS. 2B and 2C; however, FIG. 2B illustrates the 2-bit memory in a forward reading method, and FIG. 2C illustrates the 2-bit memory in a reverse reading method, both of which are described below.
Referring to FIGS. 2B and 2C, a high voltage, or programming voltage, may be applied to either a junction between a transistor type control gate 33 and a source electrode 32 or a junction between the control gate 33 and a drain electrode 34. Thereafter, electrons are injected into a channel formed in SiN at a lower edge of the control gate 33, which is adjacent to the source electrode 32 or the drain electrode 34, using a channel hot electron injection (CHEI) method. A voltage is applied to the other junction to read data in a reverse method.
Referring to FIGS. 2A and 2B, the line graph f1 illustrates a relationship between the voltage VDS between the source and drain electrodes 32, 34 and the threshold voltage VT in a forward reading method, where voltage is applied in a reading operation to the junction to which the high voltage, or programming voltage, has been applied. FIG. 2B illustrates a channel, wherein electrons trapped in the SiN exist in an upper portion of the channel at an end of the channel adjacent to the electrode to which the voltage is not applied. In FIG. 2B, since the voltage is applied to the source electrode 32, electrons are trapped in the SiN at an end of the channel adjacent the drain electrode 34. FIG. 2B illustrates low threshold voltage characteristics.
Referring to FIG. 2A, the line graph f2 illustrates a relationship between the voltage VDS between the source and drain electrodes 32, 34 and the threshold voltage VT in a reverse reading method, where a voltage is applied to a junction other than a junction to which the programming voltage has been applied. Here, FIG. 2C illustrates a channel, wherein electrons trapped in the SiN exist at an upper portion of the channel adjacent to the electrode to which the voltage has been applied, in this case the drain electrode 34. FIG. 2C illustrates a high threshold voltage VT in a programming state.
Such 2-bit memory has the advantages of reducing process costs by not increasing the integration of the conventional semiconductor memory and using relatively simple processes. However, it is difficult to obtain stable 2-bit memory characteristics due to the horizontal distribution of charges, which are trapped by an asymmetry storing method, and due to storage of the charges when using the device.
In addition, in the conventional SONOS type flash memory, a width of the channels is reduced to improve the integration of the memory; however, it is difficult to improve the integration due to technical limitations in semiconductor device manufacturing processes.
FIG. 3 illustrates a schematic sectional view of a conventional programming method for an EEPROM. A programming voltage VPP is applied to a gate electrode 57, and a source electrode 53, a drain electrode 55, and a P-bulk 51 are grounded by a metal contact method. Accordingly, electrons are transferred from the P-bulk 51 to a tunnel oxide layer 54 by Fowler-Nordheim tunneling, and are captured in a nitride layer 56 serving as a floating gate. In this way, the memory cell is programmed. Here, reference numeral 58 denotes an ONO layer.
FIGS. 4A and 4B illustrate a conventional erasing method for an EEPROM.
Referring to FIG. 4A, a negative programming voltage −VPP is applied to a gate electrode 67, and a source electrode 63, a drain electrode 65, and a P-bulk 61 are grounded as in the case of the programming method. Holes are injected from the P-bulk 61 to a tunnel oxide layer 64 and electrons captured in a nitride layer 66 serving as a floating gate are compensated. Therefore, the memory cell is erased. Here, reference numeral 68 denotes an ONO layer.
FIG. 4B illustrates another conventional erasing method for an EEPROM. Here, the method of FIG. 4B forms a pocket well and applies a voltage to the pocket well instead of applying a negative voltage to a gate electrode.
Referring to FIG. 4B, a pocket p-well 71b is formed in an n-type bulk 71. In this case, a gate electrode 77 is grounded while an erasing voltage VPP is applied to a source electrode 73, a drain electrode 75, the pocket p-well 71b, and the n-type well 71a by a metal contact method. Accordingly, charges stored in a nitride layer 76 are erased. In FIG. 4B, reference numeral 74 denotes a tunnel oxide layer and reference numeral 78 denotes an ONO layer.
The differences between the programming and erasing methods in the floating gate flash memory and the SONOS flash memory are as follows. Since the floating gate is formed of conductive polymers, a specific voltage is applied to the floating gate according to a voltage condition, and electrons and holes are injected to the floating gate according to the potential difference between the voltage applied to the floating gate and a bulk or source electrode. Thus, charges move substantially between a substrate and the floating gate.
However, since the ONO layer is formed of a nonconductive material, the voltage, which is applied according to a thickness ratio of the nitride layer or the oxide layer of the ONO layer, is distributed between the gate and the nitride layer, or between the nitride layer and the silicon substrate. Thus, electrons or holes may be injected from the silicon substrate, and holes or electrons may be reversely injected from the gate, so that programming and erasing efficiencies may be reduced. In particular, in a case where a positive voltage is applied to the gate electrode in a programming process and electrons are injected from the substrate, holes are unlikely to be reversely injected from the n-type gate electrode. However, in a case where a negative voltage is applied to the gate electrode in an erasing process and holes are injected from the substrate, electrons are likely to be reversely injected from the n-type gate electrode thereby decreasing the erasing efficiency.